1. Field of the Invention
The present invention relates to a clock signal distribution circuit, and more particularly, to a clock signal distribution circuit for distributing a clock signal at high speed and with less phase displacement on a large scale integrated circuit.
2. Related Art
As the large scale integrated circuit (hereinafter to be referred to as LSI) is formed into a larger scale and the operating frequencies increase, the relative phase displacement between the clock signals distributed on LSI, or so-called clock skew has become a large problem. AS the synchronous type LSI operation is based on the design or premise that each part of LSI is given its timing simultaneously by the clock signal, the presence of the clock skew provides a limitation to the upper limit of the operating frequencies of the synchronous type LSI, with the result that the performance is lowered.
Heretofore, as a technique to reduce the clock skew, there is known a clock tree system having the constitution of the clock buffer and clock line in a tree form. In this clock signal distribution circuit, as shown in FIG. 1, the same clock buffer 111 in each stage of the clock tree and carrying out the design layout to make the load capacity and line resistance identical with one another, delay of the propagation route from the input end of the clock tree to each output end is made to be the same. By this step, it can be expected to make the phase difference of the clock signal at the output ends relatively small to reduce the clock skew.
However, in the clock tree system as described above, a large limitation arises in the design layout in order to align the conditions of the respective clock tree routes, and practically, due to the relations of layout with other circuits or restrictions, it is difficult to align all route conditions.
There is another problem for the clock buffer 112 of the dummy and the line inserted in the clock tree to align the conditions causes an increase in the power consumption or circuit area. Furthermore, as the clock tree system is a static skew compensation by equalization at the time of the design and layout of each clock distribution route, it is not possible to compensate the clock skew for the cause of the device deviation, temperature variation, and power supply voltage fluctuation, etc. Further, as the LSI process is shrunk, the effect of coupling with other line is also non-negligible, and it is difficult to compensate it at the time of the design layout.
On the other hand, as another technique there is known a huge buffer system for driving it with a giant clock buffer. In this clock signal distribution circuit, as shown in FIG. 2, because each destination of clock distribution is short-circuited, there can be expected an effect of mutually compensating the clock skews between the destinations of the clock distribution.
However, in the huge buffer system as described above, because all the clock distribution destinations are simultaneously caused to transit, there are required a giant clock buffer 121 and a low resistance, i.e., broad width clock line 122. Therefore, power consumption and layout area are large, and especially the application to a high speed clock distribution by more than 1 GHz in a large scale LSI in the future is difficult.
A method of carrying out the phase compensation of the clock signal dynamically, not at the time of designing but at the time of operating, includes a method of arranging the clock transmission route in a double ring form or in turning back, dynamically forming a clock signal based on the phase difference between the two clock signals transmitted through these transmission routes at each destination of clock distribution, and distributing it to be neighboring areas. This method is disclosed in Japanese Patent Application Laid-Open No.8-54957 and Japanese Patent Application Laid-Open No.9-134226.
The clock distribution system described in JP-A No.8-54957 has a single stripe circulating route formed by two sets of mutually parallel transmission routes. The same phase clock signals are transmitted an the reverse direction to each other from a certain part of this surrounding route. Also, the plural clock receiving parts are placed as optional parts on the above surrounding route, so that there is formed a clock signal forming the middle point between the variation point of the receiving clock signal from the one side transmission route and the variation point of the receiving clock signal from the other transmission route as a timing standard.
The clock distribution system described in JP-A No.9-134226 constitutes a forward transmission route part and a rearward transmission route part by turning back halfway the transmission routes for supplying the clock signals to plural ICs from the clock supply source for synchronously operating the plural ICs in a manner to make the mutual transmission routes inverse to each other. Each IC detects the phase difference between the first clock signal input from the forward transmission route part and the second clock signal input from the rearward transmission route and generates the internal clock signal by the phase difference.
In these conventional clock signal distribution circuits, phase compensation is dynamically effected at the time of the operation, and it is possible to make compensation for clock skew caused by the scattering of the device, temperature variation, and fluctuation of power supply voltage, etc.
However, as the line in the LSI a very small cross-sectional area of line, it has large line resistance and is difficult to transmit high speed clock signals by a long line extending over the whole LSI. Accordingly, it is extremely difficult to apply the above technique to a high speed clock distribution of more than 1 GHz in the large scale LSI, especially by the future micro-process of no more than 0.1 .mu.m.